A continuing demand exists for increases in both the performance and integration levels of semiconductor devices. Consistent with this demand, efforts are ongoing to increase the capacitance per unit area of capacitors, thereby allowing the capacitors to be scaled down in size in order to provide increased integration levels. Additionally, efforts are also underway to increase the breakdown voltage of the capacitors in order to improve the performance and/or the reliability of the semiconductor device. Various of these efforts for providing improved capacitors have focused on reducing the thickness of the dielectric layer of the capacitor.
One widely used dielectric layer is a silicon oxide layer that has a dielectric constant of approximately 3.9. When the thickness of such a dielectric layer is reduced, it may result in increased capacitor leakage current. In particular, when the thickness of the silicon oxide layer is reduced below approximately 50 Angstroms, direct tunneling (as opposed to Fowler-Nordheim tunneling) becomes the dominant breakdown mechanism as carriers may move to the electrode through a forbidden gap of the silicon oxide layer. As a result of this direct tunneling phenomena, the leakage current of the capacitor increases. In order to provide thin dielectric layers that maintain a desired level of capacitance without a corresponding increase in the leakage current, high-k dielectric layers have been employed that have a relatively high dielectric constant.
The electrodes of capacitors used in semiconductor devices are often formed of polysilicon. However, polysilicon electrodes may sometimes be inappropriate in capacitors that include high-k dielectric layers, as high-k dielectric layers may exhibit a relatively low energy band gap as compared to conventional silicon oxide dielectric layers. As a result, capacitors that include polysilicon electrodes and a high-k-dielectric layer may exhibit increased leakage currents due to the relatively low energy barrier between the polysilicon electrode and the high-k dielectric layer. In order to avoid this increase in the leakage currents, replacement of the polysilicon electrodes with metal electrodes has been proposed as the metal layer may have a higher work function than that of the polysilicon layer.
A next generation dynamic random access memory (DRAM) devices with a minimum line width of 40 to 90 nm may, for example, need a cell capacitor having about 25 fF of capacitance (C) or more in order to reduce a soft error rate due to alpha particles. As shown in FIG. 1, assuming that the height (H) of the storage node electrode of certain conventional cell capacitors is 3 um, the dielectric layer of the cell capacitor must have an equivalent oxide thickness (EOT) of less than 12 Angstroms to provide the 25 fF of capacitance.
Both a single high-k dielectric layer formed as a tantalum oxide (Ta2O5) layer and a double high-k dielectric layer formed as a titanium oxide (TiO2) layer and a hafnium oxide (HfO2) layer have been widely used as the dielectric layer in conventional DRAM cell capacitors. Titanium nitride layers have been used to form the electrodes of such conventional DRAM cell capacitors. As illustrated in the graph FIG. 2, even when the dielectric layer of the cell capacitor is formed of a tantalum oxide layer having an EOT of 16 Angstroms, the cell capacitor may exhibit a leakage current density (IL) of more than 1×10−5 A/cm2 at 1 V of applied voltage (Va). Likewise, even when the dielectric layer of the cell capacitor is a double high-k dielectric layer formed of a titanium oxide layer and a hafnium oxide layer (which dielectric layer has an EOT of 9 Angstroms), the cell capacitor still exhibits a leakage current density (IL) of more than 1×10−2 A/cm2 at 1 V of applied voltage (Va) as illustrated in the graph of FIG. 2.